/***************************************************************************//**
* \file cyip_smif_v4.h
*
* \brief
* SMIF IP definitions
*
********************************************************************************
* \copyright
* (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYIP_SMIF_V4_H_
#define _CYIP_SMIF_V4_H_

#include "cyip_headers.h"

/*******************************************************************************
*                                     SMIF
*******************************************************************************/

#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SECTION_SIZE 0x00000100UL
#define SMIF_SMIF_BRIDGE_SECTION_SIZE           0x00010000UL
#define SMIF_CORE_SMIF_CRYPTO_SECTION_SIZE      0x00000080UL
#define SMIF_CORE_DEVICE_SECTION_SIZE           0x00000080UL
#define SMIF_CORE_SECTION_SIZE                  0x00010000UL
#define SMIF_SECTION_SIZE                       0x00040000UL

/**
  * \brief 'Remap regions' which define how XIP accesses can be remapped into SMIF physical spaces (SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION)
  */
typedef struct {
  __IOM uint32_t CTL;                           /*!< 0x00000000 Control bits for remap region */
   __IM uint32_t RESERVED[3];
  __IOM uint32_t ADDR;                          /*!< 0x00000010 Base address of remap region */
  __IOM uint32_t MASK;                          /*!< 0x00000014 Mask value to be paired with ADDR */
  __IOM uint32_t SMIF0_REMAP;                   /*!< 0x00000018 Base address for remaps into SMIF0 physical memory space */
  __IOM uint32_t SMIF1_REMAP;                   /*!< 0x0000001C Base address for remaps into SMIF1 physical memory space */
   __IM uint32_t RESERVED1[56];
} SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_Type;      /*!< Size = 256 (0x100) */

/**
  * \brief AXI/AHB interleaving and FOTA bridge (SMIF_SMIF_BRIDGE)
  */
typedef struct {
  __IOM uint32_t CTL;                           /*!< 0x00000000 Global control registers for the bridge */
   __IM uint32_t RESERVED[1023];
        SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_Type SMIF_REMAP_REGION[8]; /*!< 0x00001000 'Remap regions' which define how XIP accesses can be remapped
                                                                into SMIF physical spaces */
   __IM uint32_t RESERVED1[14848];
} SMIF_SMIF_BRIDGE_Type;                        /*!< Size = 65536 (0x10000) */

/**
  * \brief Cryptography registers (one set for each key) (SMIF_CORE_SMIF_CRYPTO)
  */
typedef struct {
  __IOM uint32_t CRYPTO_CMD;                    /*!< 0x00000000 Cryptography command */
  __IOM uint32_t CRYPTO_ADDR;                   /*!< 0x00000004 Cryptography base address */
  __IOM uint32_t CRYPTO_MASK;                   /*!< 0x00000008 Cryptography mask */
  __IOM uint32_t CRYPTO_SUBREGION;              /*!< 0x0000000C Cryptography subregion disable */
   __IM uint32_t RESERVED[4];
  __IOM uint32_t CRYPTO_INPUT0;                 /*!< 0x00000020 Cryptography input 0 */
  __IOM uint32_t CRYPTO_INPUT1;                 /*!< 0x00000024 Cryptography input 1 */
  __IOM uint32_t CRYPTO_INPUT2;                 /*!< 0x00000028 Cryptography input 2 */
  __IOM uint32_t CRYPTO_INPUT3;                 /*!< 0x0000002C Cryptography input 3 */
   __IM uint32_t RESERVED1[4];
   __OM uint32_t CRYPTO_KEY0;                   /*!< 0x00000040 Cryptography key 0 */
   __OM uint32_t CRYPTO_KEY1;                   /*!< 0x00000044 Cryptography key 1 */
   __OM uint32_t CRYPTO_KEY2;                   /*!< 0x00000048 Cryptography key 2 */
   __OM uint32_t CRYPTO_KEY3;                   /*!< 0x0000004C Cryptography key 3 */
   __IM uint32_t RESERVED2[4];
  __IOM uint32_t CRYPTO_OUTPUT0;                /*!< 0x00000060 Cryptography output 0 */
  __IOM uint32_t CRYPTO_OUTPUT1;                /*!< 0x00000064 Cryptography output 1 */
  __IOM uint32_t CRYPTO_OUTPUT2;                /*!< 0x00000068 Cryptography output 2 */
  __IOM uint32_t CRYPTO_OUTPUT3;                /*!< 0x0000006C Cryptography output 3 */
   __IM uint32_t RESERVED3[4];
} SMIF_CORE_SMIF_CRYPTO_Type;                   /*!< Size = 128 (0x80) */

/**
  * \brief Device (only used for XIP acceses) (SMIF_CORE_DEVICE)
  */
typedef struct {
  __IOM uint32_t CTL;                           /*!< 0x00000000 Control */
   __IM uint32_t RESERVED;
  __IOM uint32_t ADDR;                          /*!< 0x00000008 Device region base address */
  __IOM uint32_t MASK;                          /*!< 0x0000000C Device region mask */
   __IM uint32_t RESERVED1[4];
  __IOM uint32_t ADDR_CTL;                      /*!< 0x00000020 Address control */
   __IM uint32_t RESERVED2;
  __IOM uint32_t RX_CAPTURE_CONFIG;             /*!< 0x00000028 RX capture configuration */
   __IM uint32_t RESERVED3;
   __IM uint32_t RD_STATUS;                     /*!< 0x00000030 Read status */
   __IM uint32_t RESERVED4[3];
  __IOM uint32_t RD_CMD_CTL;                    /*!< 0x00000040 Read command control */
  __IOM uint32_t RD_ADDR_CTL;                   /*!< 0x00000044 Read address control */
  __IOM uint32_t RD_MODE_CTL;                   /*!< 0x00000048 Read mode control */
  __IOM uint32_t RD_DUMMY_CTL;                  /*!< 0x0000004C Read dummy control */
  __IOM uint32_t RD_DATA_CTL;                   /*!< 0x00000050 Read data control */
  __IOM uint32_t RD_CRC_CTL;                    /*!< 0x00000054 Read Bus CRC control */
  __IOM uint32_t RD_BOUND_CTL;                  /*!< 0x00000058 Read boundary control */
   __IM uint32_t RESERVED5;
  __IOM uint32_t WR_CMD_CTL;                    /*!< 0x00000060 Write command control */
  __IOM uint32_t WR_ADDR_CTL;                   /*!< 0x00000064 Write address control */
  __IOM uint32_t WR_MODE_CTL;                   /*!< 0x00000068 Write mode control */
  __IOM uint32_t WR_DUMMY_CTL;                  /*!< 0x0000006C Write dummy control */
  __IOM uint32_t WR_DATA_CTL;                   /*!< 0x00000070 Write data control */
  __IOM uint32_t WR_CRC_CTL;                    /*!< 0x00000074 Write Bus CRC control */
   __IM uint32_t RESERVED6[2];
} SMIF_CORE_DEVICE_Type;                        /*!< Size = 128 (0x80) */

/**
  * \brief Serial Memory Interface (SMIF_CORE)
  */
typedef struct {
  __IOM uint32_t CTL;                           /*!< 0x00000000 Control */
   __IM uint32_t STATUS;                        /*!< 0x00000004 Status */
  __IOM uint32_t CTL2;                          /*!< 0x00000008 Control 2 */
   __IM uint32_t RESERVED;
   __IM uint32_t DLP_DELAY_TAP_SEL0;            /*!< 0x00000010 DLP Delay Tap Select Register 0 */
   __IM uint32_t DLP_DELAY_TAP_SEL1;            /*!< 0x00000014 DLP Delay Tap Select Register 1 */
  __IOM uint32_t DLP_CTL;                       /*!< 0x00000018 DLP Control Register */
   __IM uint32_t RESERVED1;
   __IM uint32_t DLP_STATUS0;                   /*!< 0x00000020 DLP Status Register 0 */
   __IM uint32_t DLP_STATUS1;                   /*!< 0x00000024 DLP Status Register 1 */
   __IM uint32_t RESERVED2[7];
   __IM uint32_t TX_CMD_FIFO_STATUS;            /*!< 0x00000044 Transmitter command FIFO status */
   __IM uint32_t TX_CMD_MMIO_FIFO_STATUS;       /*!< 0x00000048 Transmitter command MMIO FIFO status */
   __IM uint32_t RESERVED3;
   __OM uint32_t TX_CMD_MMIO_FIFO_WR;           /*!< 0x00000050 Transmitter command MMIO FIFO write */
   __IM uint32_t RESERVED4[11];
  __IOM uint32_t TX_DATA_MMIO_FIFO_CTL;         /*!< 0x00000080 Transmitter data MMIO FIFO control */
   __IM uint32_t TX_DATA_FIFO_STATUS;           /*!< 0x00000084 Transmitter data FIFO status */
   __IM uint32_t TX_DATA_MMIO_FIFO_STATUS;      /*!< 0x00000088 Transmitter data MMIO FIFO status */
   __IM uint32_t RESERVED5;
   __OM uint32_t TX_DATA_MMIO_FIFO_WR1;         /*!< 0x00000090 Transmitter data MMIO FIFO write */
   __OM uint32_t TX_DATA_MMIO_FIFO_WR2;         /*!< 0x00000094 Transmitter data MMIO FIFO write */
   __OM uint32_t TX_DATA_MMIO_FIFO_WR4;         /*!< 0x00000098 Transmitter data MMIO FIFO write */
   __OM uint32_t TX_DATA_MMIO_FIFO_WR1ODD;      /*!< 0x0000009C Transmitter data MMIO FIFO write */
   __IM uint32_t RESERVED6[8];
  __IOM uint32_t RX_DATA_MMIO_FIFO_CTL;         /*!< 0x000000C0 Receiver data MMIO FIFO control */
   __IM uint32_t RX_DATA_MMIO_FIFO_STATUS;      /*!< 0x000000C4 Receiver data MMIO FIFO status */
   __IM uint32_t RX_DATA_FIFO_STATUS;           /*!< 0x000000C8 Receiver data FIFO status */
   __IM uint32_t RESERVED7;
   __IM uint32_t RX_DATA_MMIO_FIFO_RD1;         /*!< 0x000000D0 Receiver data MMIO FIFO read */
   __IM uint32_t RX_DATA_MMIO_FIFO_RD2;         /*!< 0x000000D4 Receiver data MMIO FIFO read */
   __IM uint32_t RX_DATA_MMIO_FIFO_RD4;         /*!< 0x000000D8 Receiver data MMIO FIFO read */
   __IM uint32_t RESERVED8;
   __IM uint32_t RX_DATA_MMIO_FIFO_RD1_SILENT;  /*!< 0x000000E0 Receiver data MMIO FIFO silent read */
   __IM uint32_t RESERVED9[7];
  __IOM uint32_t SLOW_CA_CTL;                   /*!< 0x00000100 Slow cache control */
   __IM uint32_t RESERVED10;
  __IOM uint32_t SLOW_CA_CMD;                   /*!< 0x00000108 Slow cache command */
   __IM uint32_t RESERVED11[29];
  __IOM uint32_t FAST_CA_CTL;                   /*!< 0x00000180 Fast cache control */
   __IM uint32_t RESERVED12;
  __IOM uint32_t FAST_CA_CMD;                   /*!< 0x00000188 Fast cache command */
   __IM uint32_t RESERVED13[29];
        SMIF_CORE_SMIF_CRYPTO_Type SMIF_CRYPTO_BLOCK[8]; /*!< 0x00000200 Cryptography registers (one set for each key) */
  __IOM uint32_t CRC_CMD;                       /*!< 0x00000600 CRC Command */
   __IM uint32_t RESERVED14[7];
  __IOM uint32_t CRC_INPUT0;                    /*!< 0x00000620 CRC input 0 */
  __IOM uint32_t CRC_INPUT1;                    /*!< 0x00000624 CRC input 1 */
   __IM uint32_t RESERVED15[6];
   __IM uint32_t CRC_OUTPUT;                    /*!< 0x00000640 CRC output */
   __IM uint32_t RESERVED16[95];
  __IOM uint32_t INTR;                          /*!< 0x000007C0 Interrupt register */
  __IOM uint32_t INTR_SET;                      /*!< 0x000007C4 Interrupt set register */
  __IOM uint32_t INTR_MASK;                     /*!< 0x000007C8 Interrupt mask register */
   __IM uint32_t INTR_MASKED;                   /*!< 0x000007CC Interrupt masked register */
   __IM uint32_t RESERVED17[12];
        SMIF_CORE_DEVICE_Type DEVICE[4];        /*!< 0x00000800 Device (only used for XIP acceses) */
   __IM uint32_t RESERVED18[15744];
} SMIF_CORE_Type;                               /*!< Size = 65536 (0x10000) */

/**
  * \brief SMIF subsystem (bridge + 2 core SMIFs, OR no bridge and 1 core SMIF) (SMIF_STRUCT)
  */
typedef struct {
        SMIF_SMIF_BRIDGE_Type SMIF_BRIDGE;      /*!< 0x00000000 AXI/AHB interleaving and FOTA bridge */
   __IM uint32_t RESERVED[16384];
        SMIF_CORE_Type CORE[2];                 /*!< 0x00020000 Serial Memory Interface */
} SMIF_STRUCT_Type;                             /*!< Size = 262144 (0x40000) */


/* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.CTL */
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_USE_SMIF_Pos 0UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_USE_SMIF_Msk 0x3UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_INTLV_STEP_SIZE_Pos 16UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_INTLV_STEP_SIZE_Msk 0x70000UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_SMIF_SPACE_Pos 31UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_CTL_SMIF_SPACE_Msk 0x80000000UL
/* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.ADDR */
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_ADDR_ADDR_Pos 20UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_ADDR_ADDR_Msk 0x1FF00000UL
/* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.MASK */
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_MASK_MASK_Pos 20UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_MASK_MASK_Msk 0x1FF00000UL
/* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.SMIF0_REMAP */
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF0_REMAP_SMIF0_REMAP_Pos 20UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF0_REMAP_SMIF0_REMAP_Msk 0x1FF00000UL
/* SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION.SMIF1_REMAP */
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF1_REMAP_SMIF1_REMAP_Pos 20UL
#define SMIF_SMIF_BRIDGE_SMIF_REMAP_REGION_SMIF1_REMAP_SMIF1_REMAP_Msk 0x1FF00000UL


/* SMIF_SMIF_BRIDGE.CTL */
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF0_Pos 0UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF0_Msk 0x1UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF1_Pos 1UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AHB_SMIF1_Msk 0x2UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF0_Pos 8UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF0_Msk 0x100UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF1_Pos 9UL
#define SMIF_SMIF_BRIDGE_CTL_ARB_PRI_AXI_SMIF1_Msk 0x200UL
#define SMIF_SMIF_BRIDGE_CTL_ENABLED_Pos        31UL
#define SMIF_SMIF_BRIDGE_CTL_ENABLED_Msk        0x80000000UL


/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_CMD */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Msk 0x1UL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_ADDR */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_ADDR_ADDR_Pos 8UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_ADDR_ADDR_Msk 0xFFFFFF00UL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_MASK */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_MASK_MASK_Pos 8UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_MASK_MASK_Msk 0xFFFFFF00UL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_SUBREGION */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_SUBREGION_SUBREGION_DISABLE_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_SUBREGION_SUBREGION_DISABLE_Msk 0xFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT0 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_LSB_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_LSB_Msk 0xFUL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_MSB_Pos 4UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_MSB_Msk 0xFFFFFFF0UL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT1 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT1_INPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT2 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT2_INPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_INPUT3 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT3_INPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY0 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY0_KEY_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY1 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY1_KEY_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY2 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY2_KEY_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_KEY3 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY3_KEY_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT0 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT1 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT2 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL
/* SMIF_CORE_SMIF_CRYPTO.CRYPTO_OUTPUT3 */
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL
#define SMIF_CORE_SMIF_CRYPTO_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL


/* SMIF_CORE_DEVICE.CTL */
#define SMIF_CORE_DEVICE_CTL_WR_EN_Pos          0UL
#define SMIF_CORE_DEVICE_CTL_WR_EN_Msk          0x1UL
#define SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Pos      4UL
#define SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Msk      0x10UL
#define SMIF_CORE_DEVICE_CTL_DATA_SEL_Pos       8UL
#define SMIF_CORE_DEVICE_CTL_DATA_SEL_Msk       0x300UL
#define SMIF_CORE_DEVICE_CTL_MERGE_TIMEOUT_Pos  12UL
#define SMIF_CORE_DEVICE_CTL_MERGE_TIMEOUT_Msk  0x7000UL
#define SMIF_CORE_DEVICE_CTL_MERGE_EN_Pos       15UL
#define SMIF_CORE_DEVICE_CTL_MERGE_EN_Msk       0x8000UL
#define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_Pos  16UL
#define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_Msk  0x3FFF0000UL
#define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_EN_Pos 30UL
#define SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_EN_Msk 0x40000000UL
#define SMIF_CORE_DEVICE_CTL_ENABLED_Pos        31UL
#define SMIF_CORE_DEVICE_CTL_ENABLED_Msk        0x80000000UL
/* SMIF_CORE_DEVICE.ADDR */
#define SMIF_CORE_DEVICE_ADDR_ADDR_Pos          8UL
#define SMIF_CORE_DEVICE_ADDR_ADDR_Msk          0xFFFFFF00UL
/* SMIF_CORE_DEVICE.MASK */
#define SMIF_CORE_DEVICE_MASK_MASK_Pos          8UL
#define SMIF_CORE_DEVICE_MASK_MASK_Msk          0xFFFFFF00UL
/* SMIF_CORE_DEVICE.ADDR_CTL */
#define SMIF_CORE_DEVICE_ADDR_CTL_SIZE3_Pos     0UL
#define SMIF_CORE_DEVICE_ADDR_CTL_SIZE3_Msk     0x7UL
#define SMIF_CORE_DEVICE_ADDR_CTL_DIV2_Pos      8UL
#define SMIF_CORE_DEVICE_ADDR_CTL_DIV2_Msk      0x100UL
/* SMIF_CORE_DEVICE.RX_CAPTURE_CONFIG */
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_NEG_SDL_TAP_SEL_Pos 0UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_NEG_SDL_TAP_SEL_Msk 0xFUL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_POS_SDL_TAP_SEL_Pos 4UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_POS_SDL_TAP_SEL_Msk 0xF0UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_PIPELINE_NEG_DAT_Pos 16UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_PIPELINE_NEG_DAT_Msk 0x10000UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_SWAP_BYTES_Pos 17UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_SDR_SWAP_BYTES_Msk 0x20000UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_PIPELINE_POS_DAT_Pos 24UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_PIPELINE_POS_DAT_Msk 0x1000000UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_SWAP_BYTES_Pos 25UL
#define SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG_DDR_SWAP_BYTES_Msk 0x2000000UL
/* SMIF_CORE_DEVICE.RD_STATUS */
#define SMIF_CORE_DEVICE_RD_STATUS_FS_STATUS_Pos 0UL
#define SMIF_CORE_DEVICE_RD_STATUS_FS_STATUS_Msk 0xFFUL
/* SMIF_CORE_DEVICE.RD_CMD_CTL */
#define SMIF_CORE_DEVICE_RD_CMD_CTL_CODE_Pos    0UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_CODE_Msk    0xFFUL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_CODEH_Pos   8UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_CODEH_Msk   0xFF00UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_WIDTH_Pos   16UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_WIDTH_Msk   0x30000UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_DDR_MODE_Msk 0x40000UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_PRESENT2_Pos 30UL
#define SMIF_CORE_DEVICE_RD_CMD_CTL_PRESENT2_Msk 0xC0000000UL
/* SMIF_CORE_DEVICE.RD_ADDR_CTL */
#define SMIF_CORE_DEVICE_RD_ADDR_CTL_WIDTH_Pos  16UL
#define SMIF_CORE_DEVICE_RD_ADDR_CTL_WIDTH_Msk  0x30000UL
#define SMIF_CORE_DEVICE_RD_ADDR_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_RD_ADDR_CTL_DDR_MODE_Msk 0x40000UL
/* SMIF_CORE_DEVICE.RD_MODE_CTL */
#define SMIF_CORE_DEVICE_RD_MODE_CTL_CODE_Pos   0UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_CODE_Msk   0xFFUL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_CODEH_Pos  8UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_CODEH_Msk  0xFF00UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_WIDTH_Pos  16UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_WIDTH_Msk  0x30000UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_DDR_MODE_Msk 0x40000UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_PRESENT2_Pos 30UL
#define SMIF_CORE_DEVICE_RD_MODE_CTL_PRESENT2_Msk 0xC0000000UL
/* SMIF_CORE_DEVICE.RD_DUMMY_CTL */
#define SMIF_CORE_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL
#define SMIF_CORE_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL
#define SMIF_CORE_DEVICE_RD_DUMMY_CTL_PRESENT2_Pos 30UL
#define SMIF_CORE_DEVICE_RD_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL
/* SMIF_CORE_DEVICE.RD_DATA_CTL */
#define SMIF_CORE_DEVICE_RD_DATA_CTL_WIDTH_Pos  16UL
#define SMIF_CORE_DEVICE_RD_DATA_CTL_WIDTH_Msk  0x30000UL
#define SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Msk 0x40000UL
/* SMIF_CORE_DEVICE.RD_CRC_CTL */
#define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Pos 0UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Msk 0xFFUL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Pos 8UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Msk 0xFF00UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Pos 28UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Msk 0x10000000UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL
#define SMIF_CORE_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL
/* SMIF_CORE_DEVICE.RD_BOUND_CTL */
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SIZE5_Pos 0UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SIZE5_Msk 0x1FUL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Pos 16UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Msk 0x30000UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Pos 20UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Msk 0x300000UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Pos 28UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Msk 0x10000000UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_PRESENT_Pos 31UL
#define SMIF_CORE_DEVICE_RD_BOUND_CTL_PRESENT_Msk 0x80000000UL
/* SMIF_CORE_DEVICE.WR_CMD_CTL */
#define SMIF_CORE_DEVICE_WR_CMD_CTL_CODE_Pos    0UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_CODE_Msk    0xFFUL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_CODEH_Pos   8UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_CODEH_Msk   0xFF00UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_WIDTH_Pos   16UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_WIDTH_Msk   0x30000UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_DDR_MODE_Msk 0x40000UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_PRESENT2_Pos 30UL
#define SMIF_CORE_DEVICE_WR_CMD_CTL_PRESENT2_Msk 0xC0000000UL
/* SMIF_CORE_DEVICE.WR_ADDR_CTL */
#define SMIF_CORE_DEVICE_WR_ADDR_CTL_WIDTH_Pos  16UL
#define SMIF_CORE_DEVICE_WR_ADDR_CTL_WIDTH_Msk  0x30000UL
#define SMIF_CORE_DEVICE_WR_ADDR_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_WR_ADDR_CTL_DDR_MODE_Msk 0x40000UL
/* SMIF_CORE_DEVICE.WR_MODE_CTL */
#define SMIF_CORE_DEVICE_WR_MODE_CTL_CODE_Pos   0UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_CODE_Msk   0xFFUL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_CODEH_Pos  8UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_CODEH_Msk  0xFF00UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_WIDTH_Pos  16UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_WIDTH_Msk  0x30000UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_DDR_MODE_Msk 0x40000UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_PRESENT2_Pos 30UL
#define SMIF_CORE_DEVICE_WR_MODE_CTL_PRESENT2_Msk 0xC0000000UL
/* SMIF_CORE_DEVICE.WR_DUMMY_CTL */
#define SMIF_CORE_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL
#define SMIF_CORE_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL
#define SMIF_CORE_DEVICE_WR_DUMMY_CTL_RWDS_EN_Pos 17UL
#define SMIF_CORE_DEVICE_WR_DUMMY_CTL_RWDS_EN_Msk 0x20000UL
#define SMIF_CORE_DEVICE_WR_DUMMY_CTL_PRESENT2_Pos 30UL
#define SMIF_CORE_DEVICE_WR_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL
/* SMIF_CORE_DEVICE.WR_DATA_CTL */
#define SMIF_CORE_DEVICE_WR_DATA_CTL_WIDTH_Pos  16UL
#define SMIF_CORE_DEVICE_WR_DATA_CTL_WIDTH_Msk  0x30000UL
#define SMIF_CORE_DEVICE_WR_DATA_CTL_DDR_MODE_Pos 18UL
#define SMIF_CORE_DEVICE_WR_DATA_CTL_DDR_MODE_Msk 0x40000UL
/* SMIF_CORE_DEVICE.WR_CRC_CTL */
#define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL
#define SMIF_CORE_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL


/* SMIF_CORE.CTL */
#define SMIF_CORE_CTL_XIP_MODE_Pos              0UL
#define SMIF_CORE_CTL_XIP_MODE_Msk              0x1UL
#define SMIF_CORE_CTL_DESELECT_DELAY_Pos        16UL
#define SMIF_CORE_CTL_DESELECT_DELAY_Msk        0x70000UL
#define SMIF_CORE_CTL_SELECT_SETUP_DELAY_Pos    20UL
#define SMIF_CORE_CTL_SELECT_SETUP_DELAY_Msk    0x300000UL
#define SMIF_CORE_CTL_SELECT_HOLD_DELAY_Pos     22UL
#define SMIF_CORE_CTL_SELECT_HOLD_DELAY_Msk     0xC00000UL
#define SMIF_CORE_CTL_BLOCK_Pos                 24UL
#define SMIF_CORE_CTL_BLOCK_Msk                 0x1000000UL
#define SMIF_CORE_CTL_CLOCK_IF_SEL_Pos          25UL
#define SMIF_CORE_CTL_CLOCK_IF_SEL_Msk          0x2000000UL
#define SMIF_CORE_CTL_ENABLED_Pos               31UL
#define SMIF_CORE_CTL_ENABLED_Msk               0x80000000UL
/* SMIF_CORE.STATUS */
#define SMIF_CORE_STATUS_DLL_LOCKED_Pos         0UL
#define SMIF_CORE_STATUS_DLL_LOCKED_Msk         0x1UL
#define SMIF_CORE_STATUS_BUSY_Pos               31UL
#define SMIF_CORE_STATUS_BUSY_Msk               0x80000000UL
/* SMIF_CORE.CTL2 */
#define SMIF_CORE_CTL2_DLL_SPEED_MODE_Pos       0UL
#define SMIF_CORE_CTL2_DLL_SPEED_MODE_Msk       0x3UL
#define SMIF_CORE_CTL2_CLKOUT_DIV_Pos           4UL
#define SMIF_CORE_CTL2_CLKOUT_DIV_Msk           0x30UL
#define SMIF_CORE_CTL2_MDL_TAP_SEL_Pos          8UL
#define SMIF_CORE_CTL2_MDL_TAP_SEL_Msk          0xF00UL
#define SMIF_CORE_CTL2_RX_CAPTURE_MODE_Pos      20UL
#define SMIF_CORE_CTL2_RX_CAPTURE_MODE_Msk      0x300000UL
#define SMIF_CORE_CTL2_RX_CHASE_MARGIN_Pos      22UL
#define SMIF_CORE_CTL2_RX_CHASE_MARGIN_Msk      0xC00000UL
#define SMIF_CORE_CTL2_TX_SDR_EXTRA_SETUP_Pos   31UL
#define SMIF_CORE_CTL2_TX_SDR_EXTRA_SETUP_Msk   0x80000000UL
/* SMIF_CORE.DLP_DELAY_TAP_SEL0 */
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT0_TAP_SEL_Pos 0UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT0_TAP_SEL_Msk 0xFFUL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT1_TAP_SEL_Pos 8UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT1_TAP_SEL_Msk 0xFF00UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT2_TAP_SEL_Pos 16UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT2_TAP_SEL_Msk 0xFF0000UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT3_TAP_SEL_Pos 24UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL0_DATA_BIT3_TAP_SEL_Msk 0xFF000000UL
/* SMIF_CORE.DLP_DELAY_TAP_SEL1 */
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT4_TAP_SEL_Pos 0UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT4_TAP_SEL_Msk 0xFFUL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT5_TAP_SEL_Pos 8UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT5_TAP_SEL_Msk 0xFF00UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT6_TAP_SEL_Pos 16UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT6_TAP_SEL_Msk 0xFF0000UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT7_TAP_SEL_Pos 24UL
#define SMIF_CORE_DLP_DELAY_TAP_SEL1_DATA_BIT7_TAP_SEL_Msk 0xFF000000UL
/* SMIF_CORE.DLP_CTL */
#define SMIF_CORE_DLP_CTL_DLP_Pos               0UL
#define SMIF_CORE_DLP_CTL_DLP_Msk               0xFFFFUL
#define SMIF_CORE_DLP_CTL_DLP_SIZE_Pos          16UL
#define SMIF_CORE_DLP_CTL_DLP_SIZE_Msk          0xF0000UL
#define SMIF_CORE_DLP_CTL_DLP_WARNING_LEVEL_Pos 24UL
#define SMIF_CORE_DLP_CTL_DLP_WARNING_LEVEL_Msk 0xF000000UL
/* SMIF_CORE.DLP_STATUS0 */
#define SMIF_CORE_DLP_STATUS0_DATA_BIT0_Pos     0UL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT0_Msk     0x1FUL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT1_Pos     8UL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT1_Msk     0x1F00UL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT2_Pos     16UL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT2_Msk     0x1F0000UL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT3_Pos     24UL
#define SMIF_CORE_DLP_STATUS0_DATA_BIT3_Msk     0x1F000000UL
/* SMIF_CORE.DLP_STATUS1 */
#define SMIF_CORE_DLP_STATUS1_DATA_BIT4_Pos     0UL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT4_Msk     0x1FUL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT5_Pos     8UL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT5_Msk     0x1F00UL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT6_Pos     16UL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT6_Msk     0x1F0000UL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT7_Pos     24UL
#define SMIF_CORE_DLP_STATUS1_DATA_BIT7_Msk     0x1F000000UL
/* SMIF_CORE.TX_CMD_FIFO_STATUS */
#define SMIF_CORE_TX_CMD_FIFO_STATUS_USED4_Pos  0UL
#define SMIF_CORE_TX_CMD_FIFO_STATUS_USED4_Msk  0xFUL
/* SMIF_CORE.TX_CMD_MMIO_FIFO_STATUS */
#define SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Pos 0UL
#define SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk 0xFUL
/* SMIF_CORE.TX_CMD_MMIO_FIFO_WR */
#define SMIF_CORE_TX_CMD_MMIO_FIFO_WR_DATA27_Pos 0UL
#define SMIF_CORE_TX_CMD_MMIO_FIFO_WR_DATA27_Msk 0x7FFFFFFUL
/* SMIF_CORE.TX_DATA_MMIO_FIFO_CTL */
#define SMIF_CORE_TX_DATA_MMIO_FIFO_CTL_TX_TRIGGER_LEVEL_Pos 0UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_CTL_TX_TRIGGER_LEVEL_Msk 0x7UL
/* SMIF_CORE.TX_DATA_FIFO_STATUS */
#define SMIF_CORE_TX_DATA_FIFO_STATUS_USED4_Pos 0UL
#define SMIF_CORE_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
/* SMIF_CORE.TX_DATA_MMIO_FIFO_STATUS */
#define SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL
/* SMIF_CORE.TX_DATA_MMIO_FIFO_WR1 */
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1_DATA0_Pos 0UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1_DATA0_Msk 0xFFUL
/* SMIF_CORE.TX_DATA_MMIO_FIFO_WR2 */
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA0_Pos 0UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA0_Msk 0xFFUL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA1_Pos 8UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR2_DATA1_Msk 0xFF00UL
/* SMIF_CORE.TX_DATA_MMIO_FIFO_WR4 */
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA0_Pos 0UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA0_Msk 0xFFUL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA1_Pos 8UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA1_Msk 0xFF00UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA2_Pos 16UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA2_Msk 0xFF0000UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA3_Pos 24UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR4_DATA3_Msk 0xFF000000UL
/* SMIF_CORE.TX_DATA_MMIO_FIFO_WR1ODD */
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1ODD_DATA0_Pos 0UL
#define SMIF_CORE_TX_DATA_MMIO_FIFO_WR1ODD_DATA0_Msk 0xFFUL
/* SMIF_CORE.RX_DATA_MMIO_FIFO_CTL */
#define SMIF_CORE_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Pos 0UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Msk 0x7UL
/* SMIF_CORE.RX_DATA_MMIO_FIFO_STATUS */
#define SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL
/* SMIF_CORE.RX_DATA_FIFO_STATUS */
#define SMIF_CORE_RX_DATA_FIFO_STATUS_USED4_Pos 0UL
#define SMIF_CORE_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
#define SMIF_CORE_RX_DATA_FIFO_STATUS_RX_SR_USED_Pos 8UL
#define SMIF_CORE_RX_DATA_FIFO_STATUS_RX_SR_USED_Msk 0x100UL
/* SMIF_CORE.RX_DATA_MMIO_FIFO_RD1 */
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_DATA0_Pos 0UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_DATA0_Msk 0xFFUL
/* SMIF_CORE.RX_DATA_MMIO_FIFO_RD2 */
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA0_Pos 0UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA0_Msk 0xFFUL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA1_Pos 8UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD2_DATA1_Msk 0xFF00UL
/* SMIF_CORE.RX_DATA_MMIO_FIFO_RD4 */
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA0_Pos 0UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA0_Msk 0xFFUL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA1_Pos 8UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA1_Msk 0xFF00UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA2_Pos 16UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA2_Msk 0xFF0000UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA3_Pos 24UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD4_DATA3_Msk 0xFF000000UL
/* SMIF_CORE.RX_DATA_MMIO_FIFO_RD1_SILENT */
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Pos 0UL
#define SMIF_CORE_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL
/* SMIF_CORE.SLOW_CA_CTL */
#define SMIF_CORE_SLOW_CA_CTL_WAY_Pos           16UL
#define SMIF_CORE_SLOW_CA_CTL_WAY_Msk           0x30000UL
#define SMIF_CORE_SLOW_CA_CTL_SET_ADDR_Pos      24UL
#define SMIF_CORE_SLOW_CA_CTL_SET_ADDR_Msk      0x3000000UL
#define SMIF_CORE_SLOW_CA_CTL_PREF_EN_Pos       30UL
#define SMIF_CORE_SLOW_CA_CTL_PREF_EN_Msk       0x40000000UL
#define SMIF_CORE_SLOW_CA_CTL_ENABLED_Pos       31UL
#define SMIF_CORE_SLOW_CA_CTL_ENABLED_Msk       0x80000000UL
/* SMIF_CORE.SLOW_CA_CMD */
#define SMIF_CORE_SLOW_CA_CMD_INV_Pos           0UL
#define SMIF_CORE_SLOW_CA_CMD_INV_Msk           0x1UL
/* SMIF_CORE.FAST_CA_CTL */
#define SMIF_CORE_FAST_CA_CTL_WAY_Pos           16UL
#define SMIF_CORE_FAST_CA_CTL_WAY_Msk           0x30000UL
#define SMIF_CORE_FAST_CA_CTL_SET_ADDR_Pos      24UL
#define SMIF_CORE_FAST_CA_CTL_SET_ADDR_Msk      0x3000000UL
#define SMIF_CORE_FAST_CA_CTL_PREF_EN_Pos       30UL
#define SMIF_CORE_FAST_CA_CTL_PREF_EN_Msk       0x40000000UL
#define SMIF_CORE_FAST_CA_CTL_ENABLED_Pos       31UL
#define SMIF_CORE_FAST_CA_CTL_ENABLED_Msk       0x80000000UL
/* SMIF_CORE.FAST_CA_CMD */
#define SMIF_CORE_FAST_CA_CMD_INV_Pos           0UL
#define SMIF_CORE_FAST_CA_CMD_INV_Msk           0x1UL
/* SMIF_CORE.CRC_CMD */
#define SMIF_CORE_CRC_CMD_START_Pos             0UL
#define SMIF_CORE_CRC_CMD_START_Msk             0x1UL
#define SMIF_CORE_CRC_CMD_CONTINUE_Pos          1UL
#define SMIF_CORE_CRC_CMD_CONTINUE_Msk          0x2UL
/* SMIF_CORE.CRC_INPUT0 */
#define SMIF_CORE_CRC_INPUT0_INPUT_Pos          0UL
#define SMIF_CORE_CRC_INPUT0_INPUT_Msk          0xFFFFFFFFUL
/* SMIF_CORE.CRC_INPUT1 */
#define SMIF_CORE_CRC_INPUT1_INPUT_Pos          0UL
#define SMIF_CORE_CRC_INPUT1_INPUT_Msk          0xFFFFFFFFUL
/* SMIF_CORE.CRC_OUTPUT */
#define SMIF_CORE_CRC_OUTPUT_CRC_OUTPUT_Pos     0UL
#define SMIF_CORE_CRC_OUTPUT_CRC_OUTPUT_Msk     0xFFUL
/* SMIF_CORE.INTR */
#define SMIF_CORE_INTR_TR_TX_REQ_Pos            0UL
#define SMIF_CORE_INTR_TR_TX_REQ_Msk            0x1UL
#define SMIF_CORE_INTR_TR_RX_REQ_Pos            1UL
#define SMIF_CORE_INTR_TR_RX_REQ_Msk            0x2UL
#define SMIF_CORE_INTR_XIP_ALIGNMENT_ERROR_Pos  2UL
#define SMIF_CORE_INTR_XIP_ALIGNMENT_ERROR_Msk  0x4UL
#define SMIF_CORE_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL
#define SMIF_CORE_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
#define SMIF_CORE_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL
#define SMIF_CORE_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
#define SMIF_CORE_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL
#define SMIF_CORE_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL
#define SMIF_CORE_INTR_DLP_FAIL_Pos             8UL
#define SMIF_CORE_INTR_DLP_FAIL_Msk             0x100UL
#define SMIF_CORE_INTR_DLP_WARNING_Pos          12UL
#define SMIF_CORE_INTR_DLP_WARNING_Msk          0x1000UL
#define SMIF_CORE_INTR_DLL_LOCK_Pos             13UL
#define SMIF_CORE_INTR_DLL_LOCK_Msk             0x2000UL
#define SMIF_CORE_INTR_DLL_UNLOCK_Pos           14UL
#define SMIF_CORE_INTR_DLL_UNLOCK_Msk           0x4000UL
#define SMIF_CORE_INTR_CRC_ERROR_Pos            16UL
#define SMIF_CORE_INTR_CRC_ERROR_Msk            0x10000UL
#define SMIF_CORE_INTR_FS_STATUS_ERROR_Pos      17UL
#define SMIF_CORE_INTR_FS_STATUS_ERROR_Msk      0x20000UL
/* SMIF_CORE.INTR_SET */
#define SMIF_CORE_INTR_SET_TR_TX_REQ_Pos        0UL
#define SMIF_CORE_INTR_SET_TR_TX_REQ_Msk        0x1UL
#define SMIF_CORE_INTR_SET_TR_RX_REQ_Pos        1UL
#define SMIF_CORE_INTR_SET_TR_RX_REQ_Msk        0x2UL
#define SMIF_CORE_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL
#define SMIF_CORE_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL
#define SMIF_CORE_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL
#define SMIF_CORE_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
#define SMIF_CORE_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL
#define SMIF_CORE_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
#define SMIF_CORE_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL
#define SMIF_CORE_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL
#define SMIF_CORE_INTR_SET_DLP_FAIL_Pos         8UL
#define SMIF_CORE_INTR_SET_DLP_FAIL_Msk         0x100UL
#define SMIF_CORE_INTR_SET_DLP_WARNING_Pos      12UL
#define SMIF_CORE_INTR_SET_DLP_WARNING_Msk      0x1000UL
#define SMIF_CORE_INTR_SET_DLL_LOCK_Pos         13UL
#define SMIF_CORE_INTR_SET_DLL_LOCK_Msk         0x2000UL
#define SMIF_CORE_INTR_SET_DLL_UNLOCK_Pos       14UL
#define SMIF_CORE_INTR_SET_DLL_UNLOCK_Msk       0x4000UL
#define SMIF_CORE_INTR_SET_CRC_ERROR_Pos        16UL
#define SMIF_CORE_INTR_SET_CRC_ERROR_Msk        0x10000UL
#define SMIF_CORE_INTR_SET_FS_STATUS_ERROR_Pos  17UL
#define SMIF_CORE_INTR_SET_FS_STATUS_ERROR_Msk  0x20000UL
/* SMIF_CORE.INTR_MASK */
#define SMIF_CORE_INTR_MASK_TR_TX_REQ_Pos       0UL
#define SMIF_CORE_INTR_MASK_TR_TX_REQ_Msk       0x1UL
#define SMIF_CORE_INTR_MASK_TR_RX_REQ_Pos       1UL
#define SMIF_CORE_INTR_MASK_TR_RX_REQ_Msk       0x2UL
#define SMIF_CORE_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL
#define SMIF_CORE_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL
#define SMIF_CORE_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL
#define SMIF_CORE_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
#define SMIF_CORE_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL
#define SMIF_CORE_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
#define SMIF_CORE_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL
#define SMIF_CORE_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL
#define SMIF_CORE_INTR_MASK_DLP_FAIL_Pos        8UL
#define SMIF_CORE_INTR_MASK_DLP_FAIL_Msk        0x100UL
#define SMIF_CORE_INTR_MASK_DLP_WARNING_Pos     12UL
#define SMIF_CORE_INTR_MASK_DLP_WARNING_Msk     0x1000UL
#define SMIF_CORE_INTR_MASK_DLL_LOCK_Pos        13UL
#define SMIF_CORE_INTR_MASK_DLL_LOCK_Msk        0x2000UL
#define SMIF_CORE_INTR_MASK_DLL_UNLOCK_Pos      14UL
#define SMIF_CORE_INTR_MASK_DLL_UNLOCK_Msk      0x4000UL
#define SMIF_CORE_INTR_MASK_CRC_ERROR_Pos       16UL
#define SMIF_CORE_INTR_MASK_CRC_ERROR_Msk       0x10000UL
#define SMIF_CORE_INTR_MASK_FS_STATUS_ERROR_Pos 17UL
#define SMIF_CORE_INTR_MASK_FS_STATUS_ERROR_Msk 0x20000UL
/* SMIF_CORE.INTR_MASKED */
#define SMIF_CORE_INTR_MASKED_TR_TX_REQ_Pos     0UL
#define SMIF_CORE_INTR_MASKED_TR_TX_REQ_Msk     0x1UL
#define SMIF_CORE_INTR_MASKED_TR_RX_REQ_Pos     1UL
#define SMIF_CORE_INTR_MASKED_TR_RX_REQ_Msk     0x2UL
#define SMIF_CORE_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL
#define SMIF_CORE_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL
#define SMIF_CORE_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL
#define SMIF_CORE_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
#define SMIF_CORE_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL
#define SMIF_CORE_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
#define SMIF_CORE_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL
#define SMIF_CORE_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL
#define SMIF_CORE_INTR_MASKED_DLP_FAIL_Pos      8UL
#define SMIF_CORE_INTR_MASKED_DLP_FAIL_Msk      0x100UL
#define SMIF_CORE_INTR_MASKED_DLP_WARNING_Pos   12UL
#define SMIF_CORE_INTR_MASKED_DLP_WARNING_Msk   0x1000UL
#define SMIF_CORE_INTR_MASKED_DLL_LOCK_Pos      13UL
#define SMIF_CORE_INTR_MASKED_DLL_LOCK_Msk      0x2000UL
#define SMIF_CORE_INTR_MASKED_DLL_UNLOCK_Pos    14UL
#define SMIF_CORE_INTR_MASKED_DLL_UNLOCK_Msk    0x4000UL
#define SMIF_CORE_INTR_MASKED_CRC_ERROR_Pos     16UL
#define SMIF_CORE_INTR_MASKED_CRC_ERROR_Msk     0x10000UL
#define SMIF_CORE_INTR_MASKED_FS_STATUS_ERROR_Pos 17UL
#define SMIF_CORE_INTR_MASKED_FS_STATUS_ERROR_Msk 0x20000UL


#endif /* _CYIP_SMIF_V4_H_ */


/* [] END OF FILE */
